Presentations
https://imec-publications.be/handle/20.500.12860/6
2024-03-28T14:03:13ZDesign of High-efficiency Visible-Spectrum SiN Grating Coupler Based on Amorphous Silicon Overlay
https://imec-publications.be/handle/20.500.12860/40867.2
Design of High-efficiency Visible-Spectrum SiN Grating Coupler Based on Amorphous Silicon Overlay
Ebrahimipour, Mohammadjavad; Yurtsever, Gunay; Van Dorpe, Pol
Design of high-efficiency visible-spectrum silicon nitride grating couplers, compatible with CMOS fabrication are proposed. The design is based on amorphous-silicon overlay and distributed-Bragg-reflectors. We simulated 74% and 79% efficiency for 638 nm and 780 nm.
2022-07-24T00:00:00ZGate-First High-k/Metal Gate FinFET for advanced DRAM peripheral transistors
https://imec-publications.be/handle/20.500.12860/40955.2
Gate-First High-k/Metal Gate FinFET for advanced DRAM peripheral transistors
Dupuy, Emmanuel; Capogreco, Elena; Dentoni Litta, Eugenio; Tao, Zheng; Sebaai, Farid; Spessot, Alessio; Horiguchi, Naoto
We report on the patterning of 3D FinFET gates following a gate-first (GF) high-k/metal gate (HKMG) integration. This unconventional GF approach in FinFET fabrication is driven by specific requirements for next generation dynamic random-access memory (DRAM) peripheral transistors. DRAM periphery transistors must be compatible with DRAM process specifications, which implies low cost of ownership and resistance to an extra-long DRAM anneal [1]. With that respect the GF integration was promoted in comparison with the conventional gate last approach used for advanced high-performance logic FinFET devices.
Gate-first patterning in this study consists in etching directly a 150 nm n+ poly-Si / 3 nm TiN / 2.2 nm HfO2 / 1.2nm SiO2 gate stack with 45 nm height Si fin topography and at scaled dimensions for the gate (CPP=110nm, Lg=30nm) and fin (pitch=45nm and width= 10nm) as shown in Figure 1. The doped poly Si is meant as a gate electrode, TiN as a work function metal, and HfO2 as a high-k gate dielectric for NMOS and PMOS transistors. The main challenges of the gate etch process are to obtain a straight gate profile and avoid fin attack (breakthrough of HfO2), TiN/HfO2 undercut, within wafer gate CD/Profile non-uniformities and lastly corner residues between gate and fin. While GF HKMG etch has been widely reported for planar logic transistors [2-3], there is a lack of literature regarding the FinFET architecture.
In this work, we have investigated different halogen-based plasma chemistries to etch this complex gate stack. Development of the gate etch process has followed two approaches. The first one relies on fluorine-based plasmas to etch the Si/TiN gates selectively to high-k gate dielectric that covers the fins. It has been initially favored thanks to an excellent selectivity to HfO2. However, severe limitations in terms of litho-etch bias and gate CD/profile control can be observed due to micro loading (Figure 2). Increasing gate CD at litho was tried as an alternative to compensate gate CD losses but sidewall roughness, strong bottom gate tapering and TiN undercut remain problematic. To overcome these difficulties, a second approach was proposed using the combination of two etch chemistries: fluorine-based plasma for the doped Si main etch (ME) and bromine-based plasmas for the soft-landing (SL) and over-etch (OE) steps of the gate patterning. A SL process based on HBr/O2/Cl2 chemistry, and a bias pulsing plasma was demonstrated without fin attack and descent gate profile thanks to an optimized selectivity to HfO2 and a more robust passivation layer on the sidewalls of the gate (Figure.3). Improvement of the hard mask open (HMO) and ME steps is also reported in terms of critical dimension (CD) control, within wafer CD uniformity, etch depth uniformity, selectivity, and profile. Last, an isotropic HfO2 etch based on a BCl3/Cl2 cyclic process was demonstrated without fin recess and residues (figure2). We show that a wet clean is needed before the HK etch to remove poly-Si/TiN etch by-products generated by HBr/O2/Cl2 based plasma.
[1] A. Spessot et al., Phys. Status Solidi A, vol. 213, no. 2, pp. 245–254, Feb. 2016.
[2] A. Le Gouil et al., Journal of Vacuum Science & Technology B 25, 767 (2007).
[3] O. Luere et al. Journal of Vacuum Science & Technology B 29, 011024 (2011).
2022-09-20T00:00:00ZAl3Sc thin films as alternative interconnect metallization
https://imec-publications.be/handle/20.500.12860/40549.2
Al3Sc thin films as alternative interconnect metallization
Soulie, Jean-Philippe; Adelmann, Christoph; Swerts, Johan; Tokei, Zsolt
New conductor materials are explored to replace Cu, W, or Co for interconnect metallization. Binary and ternary intermetallics are of particular interest to replace elemental metals in the latest research. Transition metal aluminides are amongst the intermetallics with potential as alternative metals in scaled interconnects, especially NiAl [1, 2], Al3Sc [3], or Al2Cu [4]. In this paper, we report on the resistivity of the Al3Sc compound and its complex dependence on thickness and composition. We explore routes to scale thickness below 10nm while maintaining low resistivity.
AlxSc films have been deposited (with x between 20 to 30 at.% Al) and annealed up to 600oC in H2. A clear drop in resistivity is observed after annealing at 400oC in Figure 1. A resistivity minimum at 25 at.% Sc indicated the presence of order in the films, confirmed by XRD. The lowest resistivity was found to be as low as 12.5 Ωcm for stoichiometric 24 nm thick Al3Sc films (cf. bulk 7 Ωcm [5]) after a 500oC post deposition anneal (PDA) in H2.
The film thickness dependence of the Al3Sc resistivity is shown in Figure 2, both as deposited and after annealing up to 600oC. Two regimes could be distinguished after annealing, analogous to the Ni-Al system [2]: for films thicker than 10 nm, the resistivity decreased strongly upon annealing, with little dependence on film thickness. However, for thinner films, the resistivity increased strongly, and the effect of annealing was weak.
Compositional depth profiling showed a complex chemical profile of the surface oxide responsible for the resistivity increase. To avoid the formation of the surface oxide layer, in-situ annealing and TaN capping without air break were implemented successfully. For thin films (< 10nm), Al3Sc however formed islands (see Figure 3) during in-situ annealing, leading to large sheet resistances (as seen with TEM, EDS and AFM).
To overcome, various in-situ deposited metals were explored as wetting layer for 7 nm of Al3Sc. Reactivity of the wetting layers with the Al3Sc film will be discussed since controlling the interface during PDA is identified as one of the key challenges to overcome.
2022-03-28T00:00:00ZIntroduction to imec's AttoLab for ultrafast kinetics of EUV exposure processes and ultra-small pitch lithography
https://imec-publications.be/handle/20.500.12860/41731.2
Introduction to imec's AttoLab for ultrafast kinetics of EUV exposure processes and ultra-small pitch lithography
Holzmeier, Fabian; Dorney, Kevin; Witting Larsen, Esben; Nuytten, Thomas; Singh, Dhirendra; van Setten, Michiel; Vanelderen, Pieter; Bargsten, Clayton; Cousin, Seth; Raymondson, Daisy; Rinard, Eric; Ward, Rod; Kapteyn, Henry; Bottcher, Stefan; Dyachenko, Oleksiy; Kremzow, Raimund; Wietstruk, Marko; Pourtois, Geoffrey; van der Heide, Paul; Petersen, John
Imec’s AttoLab is the first industrial laboratory capable of watching the ultrafast dynamics of photoresists following 13.5 nm, EUV exposure, and for emulating high-numerical-aperture (high-NA) exposure on 300-mm wafers using two-beam EUV interference. The two respective beamlines are powered by a laser-based high-harmonic generation EUV source. Its capabilities have recently been proven by imaging 20 nm pitch lines and spaces using Lloyd’s Mirror interference lithography. In parallel, time-averaged and time-resolved techniques for studying the ultrafast dynamics of photoresists after EUV exposure, coherent diffractive imaging to study resist interfaces, and more sophisticated interference lithography techniques for printing sub-22 nm pitches on full 300-mm wafers are being developed. Taking advantage of the bright and short EUV pulses now available at imec, we will be able to contribute to a smooth transition towards next generation high-NA lithography.
2021-02-22T00:00:00Z