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dc.contributor.authorHellemans, Thomas
dc.contributor.authorVerreck, Devin
dc.contributor.authorArreghini, Antonio
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorRosmeulen, Maarten
dc.contributor.authorHoussa, Michel
dc.contributor.authorVan Houdt, Jan
dc.date.accessioned2025-04-10T13:32:35Z
dc.date.available2025-02-23T23:40:19Z
dc.date.available2025-04-10T13:32:35Z
dc.date.issued2024
dc.identifier.isbn979-8-3315-1636-9
dc.identifier.issnN/A
dc.identifier.otherWOS:001361822500026
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45239.2
dc.sourceWOS
dc.titleModeling the Operation of Charge Trap Flash Memory: A Monte Carlo Approach to Carrier Distribution and (De)trapping
dc.typeProceedings paper
dc.contributor.imecauthorHellemans, Thomas
dc.contributor.imecauthorVerreck, Devin
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorRosmeulen, Maarten
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.imecauthorHoussa, Michel
dc.contributor.orcidimecHellemans, Thomas::0000-0001-9870-7108
dc.contributor.orcidimecVerreck, Devin::0000-0002-3833-5880
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecRosmeulen, Maarten::0000-0002-3663-7439
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.contributor.orcidimecHoussa, Michel::0000-0003-1844-3515
dc.identifier.doi10.1109/SISPAD62626.2024.10733042
dc.identifier.eisbn979-8-3315-1635-2
dc.source.numberofpages4
dc.source.peerreviewyes
dc.source.conferenceInternational Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
dc.source.conferencedateSEP 24-27, 2024
dc.source.conferencelocationSan Jose
dc.source.journalN/A
imec.availabilityPublished - imec
dc.description.wosFundingTextThis work was supported by imec's Industrial Affiliation Program for storage memories.


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