Browsing Articles by title

A +70dBm IIP3 electrical-balance duplexer for highly-integrated tunable front-ends

van Liempd, Barend; Hershberg, Benjamin; Ariumi, Saneaki; Raczkowski, Kuba; Bink, Karl-Frederik; Karthaus, Udo; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2016)

A 0.00426 mm(2) 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Wang, Shiwei; Yang, Xiaolin; Wang, Chaohan; Vilouras, Anastasios; Mora Lopez, Carolina (2022)

A 0.47-1.6mW 5-bit 0.5-1 GS/s time-interleaved SAR ADC for low-power UWB radios

Harpe, Pieter; Busze, Benjamin; Philips, Kathleen; de Groot, Harmke (2012)

A 0.5mm² power-scalable 0.5-3.8GHz CMOS DT-SDR receiver with 2nd order RF band-pass sampler

Geis, Arnd; Ryckaert, Julien; Bos, Lynn; Vandersteen, Gerd; Rolain, Yves; Craninckx, Jan (2010)

A 0.6-V, 0.015-mm2, time-based ECG readout for ambulatory applications in 40-nm CMOS

Mohan, Rachit; Zaliasl, Samira; Gielen, Georges; Van Hoof, Chris; Yazicioglu, Refet Firat; Van Helleputte, Nick (2017)

A 0.65-to-1.4 nJ/burst 3-to-10 GHz UWB all-digital TX in 90 nm CMOS for IEEE 802.15.4a

Ryckaert, Julien; Van der Plas, Geert; De Heyn, Vincent; Desset, Claude; Van Poucke, Bart; Craninckx, Jan (2007)

A 0.8-mW 5-bit 250-MS/s time-interleaved asynchronous digital slope ADC

Harpe, Pieter; Zhou, Cui; Philips, Kathleen; de Groot, Harmke (2011)

A 0.9V 0.4-6GHz harmonic recombination SDR receiver in 28nm CMOS with HR3/HR5 and IIP2 calibration

van Liempd, Barend; Borremans, Jonathan; Martens, Ewout; Cha, Sungwoo; Suys, Hans; Verbruggen, Bob; Craninckx, Jan (2014)

A 1 V 23 GHz low-noise amplifier in 45 nm planar bulk-CMOS technology with high-Q above-IC inductors

Wang, W.C.; Huang, Z.D.; Carchon, Geert; Mercha, Abdelkarim; Decoutere, Stefaan; De Raedt, Walter; Wu, C.Y. (2009)

A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers

Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2019-03)

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm

Hershberg, Benjamin; Markulic, Nereo; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide; Craninckx, Jan (2021)

A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET

Dermit, Davide; Shrivas, Mithlesh; Bunsen, Keigo; Lagos Benites, Jorge; Craninckx, Jan; Martens, Ewout (2020)

A 1.7mW 11b 250MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS

Verbruggen, Bob; Iriguchi, Masao; Craninckx, Jan (2012)

A 1.8 pJ/b, 12.5--25 Gb/s wide range all-digital clock and data recovery circuit

Verbeke, Marijn; Rombouts, Pieter; Ramon, Hannes; Moeneclaey, Bart; Yin, Xin; Bauwelinck, Johan; Torfs, Guy (2018-02)

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS

Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2022)