Browsing Articles by title

W versus Co–Al as gate fill-metal for aggressively scaled replacement high-k/metal gate devices for (Sub-)22nm technology nodes

Veloso, Anabela; Chew, Soon Aik; Schram, Tom; Dekkers, Harold; Van Ammel, Annemie; Witters, Thomas; Tielens, Hilde; Heylen, Nancy; Devriendt, Katia; Sebaai, Farid; Brus, Stephan; Ragnarsson, Lars-Ake; Pantisano, Luigi; Eneman, Geert; Carbonell, Laure; Richard, Olivier; Favia, Paola; Geypen, Jef; Bender, Hugo; Higuchi, Yuichi; Phatak, Anup; Thean, Aaron; Horiguchi, Naoto (2013)

Wachsender Markt fur Mikrosensoren und -Aktoren

Verhaegen, Katarina (1999)

Wafer based aberration metrology for lithographic systems using overlay measurements on targets imaged from phase-shift gratings

van Haver, Sven; Coene, Wim M.J.; D'have, Koen; Geypen, Niels; Van Adrichem, Paul; de Winter, Laurens; Janssen, Augustus J.E.M.; Cheng, Shaunee (2014)

Wafer bevel protection during deep reactive ion etching

Charavel, Remy; Roig, Jaime; Altamirano Sanchez, Efrain; Van Aelst, Joke; Devriendt, Katia; Van Wichelen, Koen; Gassot, Pierre; Coppens, Peter; De Backer, Eddy (2011)

Wafer level electrical evaluation of vertical carbon nanotube bundles as a function of the growth temperature

Vereecke, Bart; van der Veen, Marleen; Sugiura, Masahito; Kashiwagi, Yusaku; Ke, Xiaoxing; Cott, Daire; Hantschel, Thomas; Huyghebaert, Cedric; Tokei, Zsolt (2013)

Wafer level optical analysis of MEMS

De Wolf, Ingrid (2009)

Wafer level response to mask deficiencies in 0.55-numerical aperture extreme ultraviolet photolithography

Melvin III, Lawrence S.; Jonckheere, Rik (2022)

Wafer scale copper direct plating on thin PVD RuTa layers: A route to enable filling 30 nm features and below?

Armini, Silvia; El-Mekki, Zaid; Nagar, Margalit; Radisic, Alex; Vereecken, Philippe (2014)

Wafer thermal desorption spectrometry in a rapid thermal processor using atmospheric pressure ionization mass spectrometry

Vereecke, Guy; Kondoh, Eiichi; Richardson, Paul; Maex, Karen; Heyns, Marc (2000)

Wafer-level hermetically sealed silicon photonic MEMS

Jo, Gaehun; Edinger, Pierre; Bleiker, Simon J.; Wang, Xiaojing; Takabayashi, Alain Yuji; Sattari, Hamed; Quack, Niels; Jezzini, Moises; Lee, Jun Su; Verheyen, Peter; Zand, Iman; Khan, Muhammad Umar; Bogaerts, Wim; Stemme, Goran; Gylfason, Kristinn B.; Niklaus, Frank (2022)

Wafer-level MEMS packaging

Parton, Els; Tilmans, Harrie (2002)

Wafer-level packaging for RF passive integration

Carchon, Geert; Linten, Dimitri; Dupuis, Olivier; Decoutere, Stefaan (2005-11)

Wafer-level packaging technology for hig-Q on-chip inductors and transmission lines

Carchon, Geert; De Raedt, Walter; Beyne, Eric (2004)

Wafer-scale Cu plating uniformity on thin Cu seed layers

Yang, Liu; Atanasova, Tanya; Radisic, Alex; Deconinck, Johan; West, Alan; Vereecken, Philippe (2013)

Wafer-scale Ge epitaxial foils grown at high growth rates and released from porous substrates for triple-junction solar cells

Depauw, Valerie; Porret, Clément; Moelants, Myriam; Vecchio, Emma; Kennes, Koen; Han, Han; Loo, Roger; Cho, Jinyoun; Courtois, Guillaume; Kurstjens, Rufi; Dessein, Kristof; Orejuela, Victor; Sanchez-Perez, Clara; Rey-Stolle, Ignacio; Garcia, Ivan (2023)

Wafer-Scale Hybrid Integration of InP DFB Lasers on Si Photonics by Flip-Chip Bonding With sub-300 nm Alignment Precision

Marinins, Aleksandrs; Hansch, Sebastian; Sar, Huseyin; Chancerel, Francois; Golshani, Negin; Wang, Hsiao-Lun; Tsiara, Artemisia; Coenen, David; Verheyen, Peter; Capuz, Giovanni; De Koninck, Yannick; Yilmaz, Ozan; Morthier, Geert; Schleicher, Filip; Jamieson, Geraldine; Smyth, Stuart; McKee, Andrew; Ban, Yoojin; Pantouvaki, Marianna; La Tulipe, Douglas Charles; Van Campenhout, Joris (2023)

Wang et al. An Optimization on the Neuronal Networks Based on the ADEX Biological Model in Terms of LUT-State Behaviors: Digital Design and Realization on FPGA Platforms (vol 11, pg 1125, 2022)

Wang, Yule; Taylan, Osman; Alkabaa, Abdulaziz S.; Ahmad, Ijaz; Tag-Eldin, Elsayed; Nazemi, Ehsan; Balubaid, Mohammed; Alqabbaa, Hanan Saud (2023)