Process optimization for sub-100-nm gate patterns using phase edge lithography

van Ingen Schenau, K.K.van Ingen SchenauVleeming, BertBertVleemingGehoel-van Ansem, W. F.W. F.Gehoel-van AnsemWong, P.P.WongVandenberghe, GeertGeertVandenberghe2021-10-142021-10-142001https://imec-publications.be/handle/20.500.12860/5737Process optimization for sub-100-nm gate patterns using phase edge lithographyProceedings paper