Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency

Chuang, Po-YaoPo-YaoChuangLorenzelli, FrancescoFrancescoLorenzelliMarinissen, Erik JanErik JanMarinissen2024-06-062023-12-142024-06-0620232768-0681WOS:001099034200010https://imec-publications.be/handle/20.500.12860/43250Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and EfficiencyProceedings paper10.1109/ITC-Asia58802.2023.10301169979-8-3503-1281-2WOS:001099034200010