Analysis of border traps in high-k gate dielectrics on high-mobility channels

Simoen, EddyEddySimoenLin, DennisDennisLinAlian, AliRezaAliRezaAlianBrammertz, GuyGuyBrammertzMerckling, ClementClementMercklingMitard, JeromeJeromeMitardClaeys, CorCorClaeys2021-10-212021-10-212013https://imec-publications.be/handle/20.500.12860/23090Analysis of border traps in high-k gate dielectrics on high-mobility channelsProceedings paper