Challenges for I/O towards the 3-nm node: Si/SiGe superlatttice I/O finFET in a horizontal nanowire technology and the increased ausceptibility of bulk finFET technology to single event latchup

Hellings, GeertGeertHellingsMertens, HansHansMertensKarp, JamesJamesKarpMaillard, PierrePierreMaillardSubirats, AlexandreAlexandreSubiratsSimoen, EddyEddySimoenSchram, TomTomSchramRagnarsson, Lars-AkeLars-AkeRagnarssonSimicic, MarkoMarkoSimicicChen, Shih-HungShih-HungChenParvais, BertrandBertrandParvaisBoudier, DDBoudierCretu, BBCretuMachillot, JJMachillotPena, VVPenaSun, SSSunYoshida, NNYoshidaKim, NNKimMocuta, AndaAndaMocutaLinten, DimitriDimitriLintenHart, MichaelMichaelHartHoriguchi, NaotoNaotoHoriguchi2021-10-252021-10-252018https://imec-publications.be/handle/20.500.12860/30870Challenges for I/O towards the 3-nm node: Si/SiGe superlatttice I/O finFET in a horizontal nanowire technology and the increased ausceptibility of bulk finFET technology to single event latchupProceedings paperhttp://www.alab.ee.nctu.edu.tw/~esd/TESDC/program.html