Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning

Sun, XiaoXiaoSunRack, MartinMartinRackVan der Plas, GeertGeertVan der PlasStucchi, MicheleMicheleStucchiDe Vos, JoeriJoeriDe VosAbsil, PhilippePhilippeAbsilRaskin, J.P.J.P.RaskinBeyne, EricEricBeyne2021-10-232021-10-232016https://imec-publications.be/handle/20.500.12860/27365Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinningProceedings paperhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7540397