Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM

Huynh Bao, TrongTrongHuynh BaoSakhare, SushilSushilSakhareRyckaert, JulienJulienRyckaertYakimets, DmitryDmitryYakimetsMercha, AbdelkarimAbdelkarimMerchaVerkest, DiederikDiederikVerkestThean, AaronAaronTheanWambacq, PietPietWambacq2021-10-222021-10-222015https://imec-publications.be/handle/20.500.12860/25408Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAMProceedings paperhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7165874