Sub-20nm gate length p-FinFETs device performance improvement using TEM/EDX and NBD based TCAD calibrations.

Eyben, PierrePierreEybenDe Keersgieter, AnAnDe KeersgieterMatagne, PhilippePhilippeMatagneChiarella, ThomasThomasChiarellaPorret, ClémentClémentPorretHikavyy, AndriyAndriyHikavyySiew, Yong KongYong KongSiewGoux, LudovicLudovicGouxMitard, JeromeJeromeMitardHoriguchi, NaotoNaotoHoriguchi2025-05-142023-07-182025-05-142023-090021-4922https://imec-publications.be/handle/20.500.12860/42171Sub-20nm gate length p-FinFETs device performance improvement using TEM/EDX and NBD based TCAD calibrations.Proceedings paperPhysicsFinFETTCADTEM/EDX