Gate influence on the layout sensitivity of Si1-xGex S/D and Si1-yCy S/D transistors, including an analytical model

Eneman, GeertGeertEnemanSimoen, EddyEddySimoenVerheyen, PeterPeterVerheyenDe Meyer, KristinKristinDe Meyer2021-10-172021-10-1720080018-9383https://imec-publications.be/handle/20.500.12860/13693Gate influence on the layout sensitivity of Si1-xGex S/D and Si1-yCy S/D transistors, including an analytical modelJournal article