Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Huynh Bao, TrongTrongHuynh BaoRyckaert, JulienJulienRyckaertSakhare, SushilSushilSakhareMercha, AbdelkarimAbdelkarimMerchaVerkest, DiederikDiederikVerkestThean, AaronAaronTheanWambacq, PietPietWambacq2021-10-232021-10-232016https://imec-publications.be/handle/20.500.12860/26760Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETsProceedings paperhttp://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2505310