Integration of GAA Monolayer MoS2 Nanosheet FETs with Gate First Process for Future 2D CFET Scaling

Xi, FengbenFengbenXiSharma, HimanshuHimanshuSharmaWu, XiangyuXiangyuWuSchram, TomTomSchramConlon, DaireDaireConlonGrubbs, Robert K.Robert K.GrubbsKumar, PawanPawanKumarNgo, Tien DatTien DatNgoGhosh, SouvikSouvikGhoshHan, FeiFeiHanvan Dorp, DennisDennisvan DorpVerreck, DevinDevinVerreckSutar, SurajitSurajitSutarSmets, QuentinQuentinSmetsLin, DennisDennisLinBanerjee, KaustuvKaustuvBanerjeeLockhart de la Rosa, Cesar JavierCesar JavierLockhart de la RosaGoux, LudovicLudovicGouxKar, Gouri SankarGouri SankarKar2025-04-142025-02-022025-04-142024979-8-3503-8814-51930-8833WOS:001349548800032https://imec-publications.be/handle/20.500.12860/45157Integration of GAA Monolayer MoS2 Nanosheet FETs with Gate First Process for Future 2D CFET ScalingProceedings paper10.1109/ESSERC62670.2024.10719449979-8-3503-8813-8WOS:001349548800032