Process optimization of low temperature silicon nitride stressor layers for improvement of device performance for 45nm technology and below

Eyckens, BrendaBrendaEyckensCollaert, NadineNadineCollaertSchaekers, MarcMarcSchaekersSleeckx, ErikErikSleeckxEneman, GeertGeertEnemanVerheyen, PeterPeterVerheyenRooyackers, RitaRitaRooyackers2021-10-162021-10-162005https://imec-publications.be/handle/20.500.12860/10447Process optimization of low temperature silicon nitride stressor layers for improvement of device performance for 45nm technology and belowOral presentation