Consideration of UFET architecture for the 5nm node and beyond logic transistor

Kumar Das, UttaUttaKumar DasEneman, GeertGeertEnemanVelampati, RaviRaviVelampatiChauhan, Y.Y.ChauhanJinesh, K.K.JineshBhattacharya, T.T.Bhattacharya2021-10-252021-10-252018https://imec-publications.be/handle/20.500.12860/31091Consideration of UFET architecture for the 5nm node and beyond logic transistorProceedings paper