Understanding the intrinsic reliability behavior of n-/p-Si and p-Ge nanowire FETs utilizing degradation maps

Vaisman Chasin, AdrianAdrianVaisman ChasinBury, ErikErikBuryFranco, JacopoJacopoFrancoKaczer, BenBenKaczerVandemaele, MichielMichielVandemaeleArimura, HiroakiHiroakiArimuraCapogreco, ElenaElenaCapogrecoWitters, LiesbethLiesbethWittersRitzenthaler, RomainRomainRitzenthalerMertens, HansHansMertensHoriguchi, NaotoNaotoHoriguchiLinten, DimitriDimitriLinten2021-10-262021-10-262018https://imec-publications.be/handle/20.500.12860/31999Understanding the intrinsic reliability behavior of n-/p-Si and p-Ge nanowire FETs utilizing degradation mapsProceedings paperhttps://ieeexplore.ieee.org/document/8614542