FPGA based real-time constrained time area optimized IIR design using digital-serial arithmetic

Vlaminck, R.R.VlaminckPletinckx, J.J.PletinckxVerschuere, StefaanStefaanVerschuereBertrem, S.S.BertremVandewege, JanJanVandewegeBoets, P.P.BoetsVanuytsel, G.G.VanuytselTemmerman, S.S.Temmerman2021-10-142021-10-142002https://imec-publications.be/handle/20.500.12860/7036FPGA based real-time constrained time area optimized IIR design using digital-serial arithmeticProceedings paper