Sub-50nm gate patterning using line-trimming with 248nm or 193nm litho

Pollentier, IvanIvanPollentierJaenen, PatrickPatrickJaenenBaerts, ChristinaChristinaBaertsRonse, KurtKurtRonse2021-10-142021-10-142002https://imec-publications.be/handle/20.500.12860/6733Sub-50nm gate patterning using line-trimming with 248nm or 193nm lithoJournal article