Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

Pawlak, BartekBartekPawlakLindsay, RichardRichardLindsaySurdeanu, RaduRaduSurdeanuStolk, PeterPeterStolkMaex, KarenKarenMaex2021-10-142021-10-142002https://imec-publications.be/handle/20.500.12860/6704Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology nodeProceedings paper