Investigation of performance improvement and gate-to-junction leakage reduction fot the 90nm CMOS gate stack architecture

Henson, KirklenKirklenHensonKubicek, StefanStefanKubicekRedolfi, AugustoAugustoRedolfiDe Meyer, KristinKristinDe MeyerJurczak, GosiaGosiaJurczakAugendre, EmmanuelEmmanuelAugendre2021-10-142021-10-142002https://imec-publications.be/handle/20.500.12860/6382Investigation of performance improvement and gate-to-junction leakage reduction fot the 90nm CMOS gate stack architectureProceedings paper