Challenges in scaling of CMOS devices towards 65nm node

Jurczak, GosiaGosiaJurczakVeloso, AnabelaAnabelaVelosoRooyackers, RitaRitaRooyackersAugendre, EmmanuelEmmanuelAugendreMertens, SofieSofieMertensRothschild, AudeAudeRothschildSchaekers, MarcMarcSchaekersLindsay, RichardRichardLindsayLauwers, AnneAnneLauwersHenson, KirklenKirklenHensonSeveri, SimoneSimoneSeveriPollentier, IvanIvanPollentierDe Keersgieter, AnAnDe Keersgieter2021-10-152021-10-152003-06https://imec-publications.be/handle/20.500.12860/7714Challenges in scaling of CMOS devices towards 65nm nodeProceedings paper