Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: demonstration of a suitable gate stack for top and bottom tier nMOS

Franco, JacopoJacopoFrancoWitters, LiesbethLiesbethWittersVandooren, AnneAnneVandoorenArimura, HiroakiHiroakiArimuraSioncke, SonjaSonjaSionckePutcha, VamsiVamsiPutchaVais, AbhitoshAbhitoshVaisXie, QiQiXieGivens, MichaelMichaelGivensTang, FuFuTangJiang, X.X.JiangSubirats, AlexandreAlexandreSubiratsVaisman Chasin, AdrianAdrianVaisman ChasinRagnarsson, Lars-AkeLars-AkeRagnarssonKaczer, BenBenKaczerLinten, DimitriDimitriLintenCollaert, NadineNadineCollaert2021-10-242021-10-242017https://imec-publications.be/handle/20.500.12860/28350Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: demonstration of a suitable gate stack for top and bottom tier nMOSProceedings paperhttp://ieeexplore.ieee.org/document/7936259