Martens, EwoutEwoutMartensParisi, AngeloAngeloParisiKankuppe Raghavendra Swamy, Anirudh PraveenAnirudh PraveenKankuppe Raghavendra SwamyCooman, AdamAdamCoomanLi, HanyueHanyueLiVan Winckel, StevenStevenVan WinckelRenukaswamy, PratapPratapRenukaswamyMoura Santana, LucasLucasMoura SantanaLagos Benites, JorgeJorgeLagos BenitesMarkulic, NereoNereoMarkulicCraninckx, JanJanCraninckx2026-07-162026-07-162026979-8-3315-8937-00193-6530https://imec-publications.be/handle/20.500.12860/59880We present a 2048× time-interleaved slope-ADC implementing 7b, 175GS/s conversion. Samplers with switched buffers are proposed to realize wideband sampling in rank 1 driven by a multi-phase clock generated by a delay line with feedforward coupling. Making the slope nonlinear compensates static nonlinearities of the hierarchical sampling network. With only 0.063mm2 in 5nm CMOS, it is the smallest ultra-high-speed ADC reported to date with an excellent energy per sample of less than 2.16pJ.engProceedings paper10.1109/isscc49663.2026.11409101WOS:001760995900074