Variable tapered pareto buffer design and implementation allowing run-time configuration for low power embedded SRAMs

Wang, HuaHuaWangMiranda, MiguelMiguelMirandaPapanikolaou, AntonisAntonisPapanikolaouCatthoor, FranckyFranckyCatthoorDehaene, WimWimDehaene2021-10-162021-10-162005-10https://imec-publications.be/handle/20.500.12860/11539Variable tapered pareto buffer design and implementation allowing run-time configuration for low power embedded SRAMsJournal article