Line edge roughness (LER) correlation and dielectric reliability with spacer-defined double patterning (SDDP) at 20nm half pitch

Siew, Yong KongYong KongSiewStucchi, MicheleMicheleStucchiVersluijs, JankoJankoVersluijsRoussel, PhilippePhilippeRousselKunnen, EddyEddyKunnenPantouvaki, MariannaMariannaPantouvakiBeyer, GeraldGeraldBeyerTokei, ZsoltZsoltTokei2021-10-192021-10-192011https://imec-publications.be/handle/20.500.12860/19777Line edge roughness (LER) correlation and dielectric reliability with spacer-defined double patterning (SDDP) at 20nm half pitchProceedings paper