Bastos, JoaoJoaoBastosFranco, JacopoJacopoFrancoO'Sullivan, BarryBarryO'SullivanHigashi, YusukeYusukeHigashiVaisman Chasin, AdrianAdrianVaisman ChasinGanguly, JishnuJishnuGangulyArimura, HiroakiHiroakiArimuraSpessot, AlessioAlessioSpessotKim, Min-SooMin-SooKimHoriguchi, NaotoNaotoHoriguchi2026-03-192026-03-192025979-8-3315-0478-61541-7026https://imec-publications.be/handle/20.500.12860/58867Performance enhancement of DRAM memory will eventually require a switch of periphery transistors from planar to finFET configuration. In this work we explore gate-stack options for thick oxide (high-voltage) transistors of DRAM periphery compatible with finFET architecture. We investigate different thick oxide interface layer processes, gate stacks and processing steps and their impact on NBTI, VFB and EOT. A defect-centered analysis enables the correlated interpretation of the trends of these electrical metrics.engProceedings paper10.1109/IRPS48204.2025.10982743WOS:001546466200009TEMPERATUREOXIDATION