Interconnect Capacitance Investigation and Optimization Under I/O Pad for ESD Protection of RF/High Speed Circuits in Micro- & Nano-scale CMOS Technology

Wu, Wei-MinWei-MinWuChen, Jie-TingJie-TingChenChen, Shih-HungShih-HungChenKer, Ming-DouMing-DouKerLinten, DimitriDimitriLintenGroeseneken, GuidoGuidoGroeseneken2021-10-292021-10-292020https://imec-publications.be/handle/20.500.12860/36352Interconnect Capacitance Investigation and Optimization Under I/O Pad for ESD Protection of RF/High Speed Circuits in Micro- & Nano-scale CMOS TechnologyProceedings paperhttps://www.esda.org/assets/Events/4cf93e2446/IEW-2020-program-1-3-2020.pdf