Triple junctions for reduced impact of offset spacer variation on CMOS device parameters

Jurczak, GosiaGosiaJurczakRooyackers, RitaRitaRooyackersDe Keersgieter, AnAnDe KeersgieterKunnen, EddyEddyKunnenHenson, KirklenKirklenHensonRichard, OlivierOlivierRichardDachs, CharlesCharlesDachs2021-10-152021-10-152004-09https://imec-publications.be/handle/20.500.12860/9105Triple junctions for reduced impact of offset spacer variation on CMOS device parametersProceedings paper