Pillar patterning of Silicon / III-V vertical nanowire FET for 7nm node and beyond

Chan, BTBTChanTao, ZhengZhengTaoAltamirano Sanchez, EfrainEfrainAltamirano SanchezVeloso, AnabelaAnabelaVelosode Marneffe, Jean-FrancoisJean-Francoisde MarneffeSingh, ArjunArjunSingh2021-10-252021-10-252018https://imec-publications.be/handle/20.500.12860/30387Pillar patterning of Silicon / III-V vertical nanowire FET for 7nm node and beyondMeeting abstract