Kim, JennaJennaKimBogdanowicz, JanuszJanuszBogdanowiczMingardi, AndreaAndreaMingardiPuttarame Gowda, PallaviPallaviPuttarame GowdaStiers, KarenKarenStiersMurakami, S.S.MurakamiKuhn, M.M.KuhnYang, HongcheonHongcheonYangMoussa, AlainAlainMoussaKim, Min-SooMin-SooKimBiesemans, SergeSergeBiesemansLeray, PhilippePhilippeLerayCharley, Anne-LaureAnne-LaureCharley2026-09-212026-09-212026978-1-5106-9908-30277-786Xhttps://imec-publications.be/handle/20.500.12860/60426Complementary FET (CFET) architectures stack nMOS and pMOS devices vertically, creating buried features that challenge conventional metrology. A critical module is the selective SiGe lateral recess, which defines the gate length and inner-spacer width and strongly impacts device performance. TEM and OCD provide valuable insight but face limitations in throughput, scalability, or sensitivity for recessed structures. We demonstrate micro-spot X-ray fluorescence (µXRF) as a non-destructive, wafer-scale method to quantify SiGe recess depth in device-relevant CFETs. Normalizing the Ge Kα signal using an on-wafer Si/SiGe reference stack isolates the lateral geometry; the normalized signal correlates strongly with top-view SEM dimensions and TEM-derived SiGe lengths (R2 ≈ 0.996). Applying this calibration across 495 dies per wafer reveals clear radial non-uniformity of the lateral recess. Repeatability and error propagation show a calibration-limited 3σ depth-resolution floor of ∼1.4 nm, with intrinsic µXRF sensitivity < 1 nm at dwell times of about one minute—indicating strong potential for future inline monitoring.engProceedings paper10.1117/12.3087689WOS:0017736898000311996-756X