Plasma process optimization for dual pattern 30nm half pitch interconnect application

Huffman, CraigCraigHuffmande Marneffe, Jean-FrancoisJean-Francoisde MarneffeDemuynck, StevenStevenDemuynckGoossens, DannyDannyGoossensBeyer, GeraldGeraldBeyerStruyf, HerbertHerbertStruyf2021-10-172021-10-172009https://imec-publications.be/handle/20.500.12860/15507Plasma process optimization for dual pattern 30nm half pitch interconnect applicationMeeting abstract