3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)

Van Olmen, JanJanVan OlmenCoenen, JensJensCoenenDehaene, WimWimDehaeneDe Meyer, KristinKristinDe MeyerHuyghebaert, CedricCedricHuyghebaertJourdain, AnneAnneJourdainKatti, GuruprasadGuruprasadKattiMercha, AbdelkarimAbdelkarimMerchaRakowski, MichalMichalRakowskiStucchi, MicheleMicheleStucchiTravaly, YoussefYoussefTravalyBeyne, EricEricBeyneSwinnen, BartBartSwinnen2021-10-182021-10-182009https://imec-publications.be/handle/20.500.12860/164073D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)Proceedings paper