3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Eyben, PierrePierreEybenRitzenthaler, RomainRomainRitzenthalerDe Keersgieter, AnAnDe KeersgieterChiarella, ThomasThomasChiarellaVeloso, AnabelaAnabelaVelosoMertens, HansHansMertensPena, VanessaVanessaPenaSantoro, GaetanoGaetanoSantoroMachillot, JeromeJeromeMachillotKim, MyungsunMyungsunKimMiyashita, ToshihikoToshihikoMiyashitaYoshida, NaomiNaomiYoshidaBender, HugoHugoBenderRichard, OlivierOlivierRichardCelano, UmbertoUmbertoCelanoParedis, KristofKristofParedisWouters, LennaertLennaertWoutersMitard, JeromeJeromeMitardHoriguchi, NaotoNaotoHoriguchi2021-10-272021-10-272019https://imec-publications.be/handle/20.500.12860/329433D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistorsProceedings paper