Gorbunov, MaximMaximGorbunovCaglar, AlicanAlicanCaglarHariharakrishnan, SivaramakrishnanSivaramakrishnanHariharakrishnanTimokhin, EvgeniiEvgeniiTimokhinvan de Burgwal, MarcelMarcelvan de BurgwalBerti, LaurentLaurentBertiThys, GeertGeertThysGaur, NidhishNidhishGaur2026-09-032026-09-032026978-3-032-14407-2978-3-032-14404-11876-1100https://imec-publications.be/handle/20.500.12860/60198For ultra deep sub-micron technologies, charge sharing affects areas beyond the standard cell dimensions. Scaling up cells to ensure no charge sharing occurs inside therefore would have a major negative impact on area efficiency. We propose a D-flip-flop based on the principles of multi-bit flip-flops with integrated majority voters for the Triple Modular Redundancy (TMR) scheme, where the internal triplicated elements respect the critical spacing requirement and the cell can be used as a intrinsic rad-hard cell that requires no additional radiation mitigation on system level. We discuss the design trade-offs and compare the performance parameters of single- and multi-bit D-flip-flops from the standard library with the designed 2-bit TMR and 1-bit (Dual Interlocked Cell-based (DICE) DFFs.engProceedings paper10.1007/978-3-032-14405-8_14WOS:001763054700014MITIGATIONSRAM