Tchouflian, PaulinePaulineTchouflianBarge, D.D.BargeHartmann, J.M.J.M.HartmannKerdilès, S.S.KerdilèsVincent, LarreyLarreyVincentFournel, FrankFrankFournelLoup, V.V.LoupHauchecorne, P.P.HauchecornePapon. A.M.Thouvard, A.A.ThouvardRichy, J.J.RichyMazel, Y.Y.MazelGauthier, N.N.GauthierFraczkiewicz, A.A.FraczkiewiczPares, G.G.ParesSchippers, DavidDavidSchippersJain, UtkarshUtkarshJainBrems, StevenStevenBremsLoo, RogerRogerLooChan, BTBTChan2026-08-252026-08-2520261873-40811369-8001https://imec-publications.be/handle/20.500.12860/60100We focus on the fabrication of a Complementary Field Effect Transistor (CFET) stack with two distinct four-periods Si/SiGe epitaxial superlattices isolated from one another by a thin thermal SiO2 layer. The structure is built using oxide-oxide wafer-to-wafer direct bonding and a Bond and Etch Back SOI (BESOI) approach to transfer the donor stack onto the receiver wafer. Key process steps of this fabrication flow are described including the superlattice epitaxial growth, the formation of the thermal oxide bonding layer, the molecular hydrophilic bonding and finally the donor wafer dismounting with extensive physical characterizations performed at each step. This process flow yields defect-free CFET channel stacks provided that the thermal oxide growth is well controlled and limited to a thickness of about 15 nm on top of each superlattice (i.e. a MDI thickness of at most 30 nm), a value compatible with the specifications of future CFET devices.engJournal article10.1016/j.mssp.2026.110826WOS:001793570300001GROWTHGEhttps://www.sciencedirect.com/science/article/pii/S1369800126004221https://www.sciencedirect.com/science/article/pii/S13698001260042211873-4081