Cu plating of through-Si vias for 3D-stacked integrated circuits

Radisic, AlexAlexRadisicLuhn, OleOleLuhnSwinnen, BartBartSwinnenBender, HugoHugoBenderDrijbooms, ChrisChrisDrijboomsDoumen, GeertGeertDoumenKellens, KristofKristofKellensRuythooren, WouterWouterRuythoorenVereecken, PhilippePhilippeVereecken2021-10-172021-10-172008https://imec-publications.be/handle/20.500.12860/14350Cu plating of through-Si vias for 3D-stacked integrated circuitsOral presentation