Gate-source-drain architecture impact on DC and performance of sub-100-nm elevated source/drain NMOS transistors

Jeamsaksiri, WutthinanWutthinanJeamsaksiriJurczak, GosiaGosiaJurczakGrau, LluisLluisGrauLinten, DimitriDimitriLintenAugendre, EmmanuelEmmanuelAugendrede Potter de ten Broeck, MurielMurielde Potter de ten BroeckRooyackers, RitaRitaRooyackersWambacq, PietPietWambacqBadenes, GonçalGonçalBadenes2021-10-152021-10-152003https://imec-publications.be/handle/20.500.12860/7688Gate-source-drain architecture impact on DC and performance of sub-100-nm elevated source/drain NMOS transistorsJournal article