Lin, Shih-Hsiang (Shane)Shih-Hsiang (Shane)LinSimicic, MarkoMarkoSimicicPantano, NicolasNicolasPantano2026-06-152026-06-1520242948-1201https://imec-publications.be/handle/20.500.12860/597192.5D/3D technologies require designers to reduce electrostatic discharge (ESD) protection of the internal I/O interfaces. To avoid over-design of ESD protection, designers require a more fundamental understanding of the ESD events that occur at this level. Here we present insights, practical guidelines and research directions for circuit designers and suppliers of bonding tools.engEditorial material10.1038/s44287-024-00071-4WOS:001625333400007