Higashi, YusukeYusukeHigashiVaranasi, AnirudhAnirudhVaranasiRoussel, PhilippePhilippeRousselSaraza Canflanca, PabloPabloSaraza CanflancaBastos, JoaoJoaoBastosGrill, AlexanderAlexanderGrillCatapano, EdoardoEdoardoCatapanoAsanovski, RubenRubenAsanovskiFranco, JacopoJacopoFrancoKaczer, BenBenKaczerVaisman Chasin, AdrianAdrianVaisman ChasinVerreck, DevinDevinVerreckRamesh, SivaSivaRameshBreuil, LaurentLaurentBreuilArreghini, AntonioAntonioArreghiniRachidi, SanaSanaRachidiJeong, YongbinYongbinJeongVan den Bosch, GeertGeertVan den BoschRosmeulen, MaartenMaartenRosmeulenDegraeve, RobinRobinDegraeve2026-03-162026-03-162025-01-01979-8-3315-0478-61541-7026https://imec-publications.be/handle/20.500.12860/588533D NAND Trench cells have been proposed for further cost reduction by achieving lateral scaling. However, further dimension scaling of the memory cells raises concerns about random telegraph noise (RTN). In this work, a physics-informed machine learning framework is applied to analyze RTN in 3D NAND Trench devices as well as gate-all-around devices. The trench device has fewer traps but with a stronger single trap impact than GAA, resulting in larger impact of total RTN. Additionally, Comphy and TCAD simulations are carried out to physically interpret the results, revealing the detrimental impact of the gate edge of the Trench structure.engProceedings paper10.1109/IRPS48204.2025.10983878WOS:001546466200199