High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level package

Podpod, ArnitaArnitaPodpodVelenis, DimitriosDimitriosVelenisPhommahaxay, AlainAlainPhommahaxayBex, PieterPieterBexFodor, FerencFerencFodorMarinissen, Erik JanErik JanMarinissenRebibis, Kenneth JuneKenneth JuneRebibisMiller, AndyAndyMillerBeyer, GeraldGeraldBeyerBeyne, EricEricBeyne2021-10-262021-10-262018https://imec-publications.be/handle/20.500.12860/31549Various Fan-Out Wafer Level Packaging (FO-WLP) approaches have been developed and established over the past years to answer the increasing need for high data rates, wide I/O count and the demand for increase function integration on package. Imec has been working on a novel 300mm FO-WLP concept that enables 20μm pitch interconnect density: Flip-Chip on FO-WLP. Major challenges and solutions are reported in this paper. Results demonstrate die placement alignment of <3μm, which is suitable to allow stacking for high density interconnect. Connections between the assembled dies were intact before and after molding.High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level packageProceedings paper10.37665/waeacen36174https://ieeexplore.ieee.org/document/8573262