Pitch walking assessment after self-aligned double patterning for the 10nm logic technology node

Zarate Rincon, FabianFabianZarate RinconVega Gonzalez, VictorVictorVega GonzalezCiofi, IvanIvanCiofiWilson, ChrisChrisWilsonvan der Veen, MarleenMarleenvan der VeenRoussel, PhilippePhilippeRousselBoemmels, JuergenJuergenBoemmelsTokei, ZsoltZsoltTokeiTorres, R.R.TorresMurphy, R.S.R.S.Murphy2021-10-232021-10-232016https://imec-publications.be/handle/20.500.12860/27654Pitch walking assessment after self-aligned double patterning for the 10nm logic technology nodeMeeting abstract