Chen, YukaiYukaiChenLofrano, MelinaMelinaLofranoMoolchandani, DikshaDikshaMoolchandaniOprins, HermanHermanOprinsVan Der Plas, GeertGeertVan Der PlasRyckaert, JulienJulienRyckaertBiswas, DwaipayanDwaipayanBiswasMyers, JamesJamesMyers2026-08-212026-08-212025979-8-3315-6786-62380-9248https://imec-publications.be/handle/20.500.12860/60081The integration of High Bandwidth Memory (HBM) stacks directly atop GPUs offers bandwidth and package density but introduces severe thermal constraints. This work presents a thermal analysis and co-optimization approach for 3D HBM-on-GPU architectures under realistic power and packaging conditions. Within a consistent simulation environment, we evaluate a suite of technology- and system-level mitigation strategies, including HBM base die removal, HBM DRAM die merging, GPU frequency scaling, and doublesided cooling. Results show that peak GPU temperature can be reduced from 141.7°C to 70.8°C, with potential for improved throughput density (performance per unit package area) over 2.5D integration. This study highlights the importance of cross-layer thermal co-design and demonstrates the viability of HBM-on-GPU 3D stacking.engProceedings paper10.1109/iedm50572.2025.11353711WOS:001701480300166