Mukherjee, ShankhaShankhaMukherjeeBizindavyi, JasperJasperBizindavyiClima, SergiuSergiuClimaXiang, YangYangXiangPopovici, Mihaela IoanaMihaela IoanaPopoviciBelmonte, AttilioAttilioBelmonteIzmailov, RomanRomanIzmailovStiers, JimmyJimmyStiersKruv, AnastasiiaAnastasiiaKruvSubhechha, SubhaliSubhaliSubhechhaDekkers, HaroldHaroldDekkersKar, Gouri SankarGouri SankarKarDe, GourabGourabDeRonchi, NicoloNicoloRonchiBelkhiri, Z.Z.BelkhiriVan den Bosch, GeertGeertVan den BoschRosmeulen, MaartenMaartenRosmeulenCatthoor, FranckyFranckyCatthoorYu, S.S.YuAfanasiev, ValeriValeriAfanasievVan Houdt, JanJanVan Houdt2026-04-212026-04-2120242380-9248https://imec-publications.be/handle/20.500.12860/59142Realization of a robust non-destructive read oper-ation (NDRO) in a dense, energy-efficient, BEOL-compatible non-volatile memory device is highly desirable for RAM applications. Though the capacitive memory window (CMW) in ferroelectric (FE) capacitors (FeCAPs) has been shown to enable a NDRO, it is currently insufficient to meet the target application requirements. In this work, we show that the CMW can be significantly improved by integrating a semi-conductor (SC) layer into a FeCAP such that the FE polarization controls the electron density and hence the capacitive response of the SC layer. We experimentally demonstrate this by adding a SC IGZO to a BEOL-compatible HZO-based FeCAP. By further optimizing the IGZO layer (thickness and composition), the IGZO/electrode interface, and enhancing the FE response of the HZO, we achieve a record high CMW ~2.63 μF/cm2 for NDRO. Moreover, we demonstrate the first CMW in scalable 3D memory devices in a NAND array con-figuration with vertically integrated IGZO/HZO layers.engProceedings paper10.1109/iedm50854.2024.10873459WOS:001692734400141