Managing Crosstalk in multi-GHz Front Side Clock for Back Side Power enabled Sub-2nm 2D/3D ICs

Dubey, PrashantPrashantDubeyZografos, OdysseasOdysseasZografosPantano, NicolasNicolasPantanoVenugopal, PriyaPriyaVenugopalKükner, HalilHalilKüknerMyers, JamesJamesMyersHellings, GeertGeertHellingsRyckaert, JulienJulienRyckaert2025-06-182025-02-032025-06-182024979-8-3315-1714-42381-3555WOS:001361814100055https://imec-publications.be/handle/20.500.12860/45169Managing Crosstalk in multi-GHz Front Side Clock for Back Side Power enabled Sub-2nm 2D/3D ICsProceedings paper10.1109/ICICDT63592.2024.10717853979-8-3315-1713-7WOS:001361814100055DELAYNOISE