Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Sakhare, SushilSushilSakharePerumkunnil, ManuManuPerumkunnilHuynh Bao, TrongTrongHuynh BaoRao, SiddharthSiddharthRaoKim, WoojinWoojinKimCrotti, DavideDavideCrottiYasin, FarrukhFarrukhYasinCouet, SebastienSebastienCouetSwerts, JohanJohanSwertsKundu, ShreyaShreyaKunduYakimets, DmitryDmitryYakimetsBaert, RogierRogierBaertOh, HyungrockHyungrockOhSpessot, AlessioAlessioSpessotMocuta, AndaAndaMocutaKar, Gouri SankarGouri SankarKarFurnemont, ArnaudArnaudFurnemont2021-10-262021-10-262018https://imec-publications.be/handle/20.500.12860/31710Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm nodeProceedings paperhttps://ieeexplore.ieee.org/document/8614637