ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable Matrix

Mei, BingfengBingfengMeiVernalde, SergeSergeVernaldeVerkest, DiederikDiederikVerkestDe Man, HugoHugoDe ManLauwereins, RudyRudyLauwereins2021-10-152021-10-152003https://imec-publications.be/handle/20.500.12860/7886ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable MatrixProceedings paper