A class of power-efficient VLSI architectures for high-speed turbo-decoding

Bougard, BrunoBrunoBougardGiulietti, AlexandreAlexandreGiuliettiVan der Perre, LiesbetLiesbetVan der PerreCatthoor, FranckyFranckyCatthoor2021-10-142021-10-142002https://imec-publications.be/handle/20.500.12860/6060A class of power-efficient VLSI architectures for high-speed turbo-decodingProceedings paper