A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

Spagnolo, AnnachiaraAnnachiaraSpagnoloVerbruggen, BobBobVerbruggenD'amico, StefanoStefanoD'amicoWambacq, PietPietWambacq2021-10-222021-10-222014https://imec-publications.be/handle/20.500.12860/24554A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOSProceedings paperhttp://ieeexplore.ieee.org/xpl/articleDeails.jsp?arnumber=6942025