SiGe selective etching to enable bottom and middle dielectric isolations for advanced gate-all-around FET architecture

Kawarazaki, HikaruHikaruKawarazakiNakano, TeppeiTeppeiNakanoIshizu, TakaakiTakaakiIshizuTanaka, TakayoshiTakayoshiTanakaLiu, WenWenLiuChen, JasonJasonChenKawashima, TomohikoTomohikoKawashimaWu, AipingAipingWuSebaai, FaridFaridSebaaiLai, Ju-GengJu-GengLaiOniki, YusukeYusukeOnikiAltamirano Sanchez, EfrainEfrainAltamirano Sanchez2025-02-102023-09-212025-02-102023-08-141662-9779https://imec-publications.be/handle/20.500.12860/42577SiGe selective etching to enable bottom and middle dielectric isolations for advanced gate-all-around FET architectureProceedings paper10.4028/p-MsGv7Q